This invention relates to computer and microprocessor based products and more particularly, to a means for preventing the loss of data from the memory as well as for preventing an erroneous transfer of data to the memory of the product upon a loss of primary power.
In computer and microprocessor based products, it is necessary to store data in a random access memory (RAM). In some cases it is necessary to maintain storage of this data even when power is off so that the data will not be lost and the operating capacity of the unit will be preserved.
One method of storing data while power is off is by the use of CMOS RAM integrated circuits powered from a battery. The CMOS RAM data storage is chosen for some products because its power consumption can usually be made very low for long term data retention. This can be accomplished by providing appropriate signals on certain pins of the integrated circuit devices by means well known to those familiar with this art. The use of the CMOS RAM for data storage, however, introduces some difficulties when it is desired to make sure that the data is preserved during power failures. These difficulties arise mostly because of the necessary sequence of events which must occur in order to preserve the data stored in the CMOS RAM. Thus the microprocessor must be given advance warning that the dc power to the system and particularly to the CMOS RAM is about to fail and that warning signal must occur early enough so that any data transfer that is to be initiated will be finished before the dc supply to the RAM has failed. Also, the RAM device must be put into the "Data Retention" mode to assure that the data is retained when less than the normal supply voltage to the RAM device is available. There must simultaneously be prevented any addressing or writing into the RAM. It will thus be evident that the data retention mode cannot be initiated until it is known that the data transfers that have already been started have been completed, otherwise partial data transfers may occur with the associated errors.
To accomplish the "Data Retention" mode, the RAM power supply must be switched from its normal dc supply which is produced from the ac power to a back-up battery supply which will be adequate to retain the data in the RAM providing ac power is restored within the time period during which the batteries can maintain their charge at a level sufficient to maintain data in the RAM. In addition to the above steps for maintaining data during power failure, it is, of course, necessary that the microprocessor be able to write to the RAM after the power has been returned but not before the RAM is enabled.
The nearest prior art consists of a system which utilizes a voltage comparator connected to the dc supply for the RAM so arranged that the comparator senses when that supply has begun to decay to the value of the ac power supply. Such an arrangement, however, does not always provide adequate time to complete data transfers already initiated as well as to place the RAM in a "Data Retention" mode after data transfers have been completed and can thus lead to incomplete transfers and associated errors that result therefrom.